Studies of the Boron Penetration in p+ Poly-Si Gate Structures
|關鍵字:||硼穿透;矽化鈷;複晶矽;氮化;電感耦合電漿;boron penetration;CoSi2;poly-Si;nitridation;inductilvely coupled plasma|
In this thesis, two new techniques are proposed to suppress the boron penetration and improve the gate oxide integrity in the p+ poly-Si gate structure. Firstly, a novel process that implants BF2+ ions into thin bilayered CoSi/amorphous-Si (a-Si) films has been introduced to form excellent cobalt silicided p+ poly-Si gates. The process utilizes the cobalt silicide layer as an implantation barrier to minimize the boron diffusion by reducing the projection range and implant-induced defects, thus resulting in smaller flat-band voltage (Vfb) shift and better characteristics of the breakdown field (Ebd) and charge to breakdown (Qbd). Moreover, the a-Si underlayer is simultaneously kept during the formation of the low-temperature self-aligned silicide (SAD) process to further block the boron diffusion and improve gate oxide integrity. Hence, the effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide into underlying Si substrates. As a result, this scheme shows good feasibility for further deep-submicron dual gate CMOS technology. However, the dielectric strength of thin gate oxide beneath cobalt polycide gate electrodes is an important issue, which has not been extensively investigated. Consequently, the reliability of thin gate oxides fabricated by implanting BF2+ ions into bilayered CoSi/a-Si films and subsequent furnace annealing has been studied as a function of cobalt silicide thickness and implantation energy. Significant degradation of gate oxide integrity and flat-band voltage shifts were found with increasing cobalt silicide thickness and annealing temperature. It is shown that although thinner cobalt silicide can result in excellent integrity of gate dielectric, it also leads to worse thermal stability at high annealing temperature. Moreover, shallower implantation depth and lower annealing temperature can reduce the boron penetration, but depletion effects in polycrystalline silicon gates are caused accordingly. Hence, appropriate process conditions, involving trade-off among CoSi2 thickness, implantation energy and annealing temperature, must be used to optimize the device performance while retaining the thin dielectric reliability. As for the trend of using low thermal-budget process in the future advanced CMOS technology, the cobalt polycide gate formed by implanting BF2+ ions into the bilayered CoSi/a-Si films and subsequent rapid thermal anneal, instead of long-term furnace annealing, has been studied. The resulting gate oxide integrity is characterized with respect to various silicide thickness and implantation energies. The samples with thinner silicide by RTA treatments possess better high-temperature stability that those by FA treatments. In addition, small flat-band voltage shifts and excellent gate oxide integrity are found for the samples by RTA, as compared to those by FA, attributable to low thermal budget and thus suppression of boron penetration. Finally, the other technique to suppress the boron penetration is nitridizing the stacked poly-Si gates by using Inductively Coupled N2 Plasma (ICNP) system to improve the gate oxide integrity. The ICNP treatments at the interfaces of stacked poly-Si films would create the nitrogen-rich layers not only at the treated poly-Si interface but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. Furthermore, the position of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and significant improvement of gate oxide reliability. However, although the samples by the ICNP treatment directly on the gate oxide possess much smaller flat-band voltage (Vfb) shifts than the samples without ICNP treatments, severe degradation of the breakdown field (Ebd) and charge to breakdown (Qbd) values was found and attributed to the severe ICP N2 plasma damage directly on the gate oxide.
|Appears in Collections:||Thesis|