Impacts of CVD Dielectric Characteristics on ULSI CMP Process and Memory Devices Performance
曾 偉 志
Wei Tsi Tseng
|關鍵字:||化學氣相沉積;介電薄膜;淺溝渠絕緣製程;氧化矽;氮化矽;富矽氧化矽;化學機械拋光;非晶矽未鍵結鍵;CVD;Dielectric;back-end-of-line dielectrics;oxide;nitride;silicon rich oxide;CMP;a-Si-like dangling bond|
整合這些多層薄膜於ULSI記憶元件製程中，發現這些薄膜將影響元件特性，O3/TEOS 所成長之氧化矽較SOG對4-T SRAM元件特性有更佳之改善，水氣與氫離子由後段製程中釋放將劣化記憶元件特性，使用富矽氧化矽於ILD、IMD及護層中可以改善SRAM、NVM之元件特性與可靠度，膜中所含非晶矽未鍵結鍵(*Si*Si3)可以有效吸附後段製程中所產生之氫、水汽等移動性離子降低對元件所造成之影響，確保記憶元件中資料儲存之可靠度；因此，降低氮化矽中氫含量亦可進一步改善元件特性與可靠度。|
From an industrial application perspective, this study systematically investigated the material characteristics of typically used ULSI back-end-of-line dielectrics and their CMP performance. The rule of INTEGRATE proposed in this study provides the optimization scheme for ULSI CVD and CMP processes with cost effectivity and promising process performance. Besides, based on results of material analysis and ULSI memory device performance, the optimal process integration scheme could be identified for the implementation of proper dielectric materials with specific characteristics into the memory devices. This also yielded better and more reliable memory device performances. In this study, the dielectric material characteristics of CVD oxide and nitride films were systematically developed and investigated. PECVD silicon rich oxide (SRO) provided an identical substrate surface for the subsequent O3/TEOS SACVD process, leading to elimination of the substrate sensitivity and hence good thickness uniformity and gap fill capability. As the Si content increased in the SRO, the extra Si atoms would be incorporated in form of Si-H bonds which eventually led to the formation of Si nanocrystals. The extra Si-H bonds inserted inside the oxide network inhibited the perfect growth of oxide locally, leading to elongated bonds and hence a tensile stress component and enhanced chemical activity in the oxide. They also enhanced electron polarizability, resulting in higher RI, higher density of a-Si-like dangling bond (*Si*Si3) and the presence of more silicon nanocrystals. Increasing the SiH4/NH3 flow ratio during PECVD nitride reactions resulted in the decreases in RI, Si:N atomic ratio, amount of hydrogen desorption, wet etch rate and CMP removal rate (R/R) as well as the increases in compressive stress, thin film density and N-H bonding density. The existence of more Si-H bonds increased the porosity of PECVD SiNx, leading to the increases in both chemical etch rate and CMP removal rate due to the lower diffusion coefficient of water or H+ in the nitrides. Advanced process integration based on the fundamental of CMP removal rate selectivity between dielectric materials was developed. By using multi-layered thin film structure (SiO2/SiNx/SiO2) with modifications in their characteristics to adjust the CMP remove rate selectivity and efficiency of polish stopper, a one-step CMP process for ULSI shallow trench isolation (STI) process was developed. Globally-planarized surface and dishing-free wide trench areas could be achieved based on this study. An integrated solution to the IMD/CMP process which included the Integral Nonuniformity, Thickness of dielectric, Efficiency of planarization, Geometry of device, Removal rate, And its variation for CMP Time Estimation (INTERGATE) was also proposed to estimate the required dielectric thickness and optimal polishing time in order to enhance the throughput and reliability of the IMD-CMP process. The implementation of the fine-tuned CVD dielectrics into ULSI memory devices exposed some potential impacts of dielectric material characteristics upon memory device performance. The incorporation of O3-TEOS oxides was shown to yield better 4-T SRAM device performance than conventional SOG process. Water diffusion from oxide and hydrogen released from nitride were both responsible for MOS device and memory device characteristics degradation. Incorporation of a PECVD-SRO underlayer improved the device characteristics and reliability of the 4-T SRAM and non-volatile memory (NVM) devices. The a-Si-like dangling bonds (*Si*Si3) in IMD films served as effective trapping centers for hydrogen or moisture and hence protected device from the attack by backend process-induced mobile charges. Thus the resistance of 4-T SRAM poly-Si load resistors and NVM floating gate device integrity were maintained at high and stable quality with minimum deviation, and improved device performance and data storage reliability could be achieved. Further improvement in memory device characteristics could be fulfilled by optimizing the characteristics of PECVD SiO2/SiNx passivation layers. PECVD nitride with the highest amount hydrogen desorption showed the most significant impact on MOS device characteristics, as well as highest NVM floating gate drift and 4-T SRAM deterioration rate.
|Appears in Collections:||Thesis|