Title: 應用於低電壓操作的假晶高電子遷移率電晶體之GaAs/ Al0.2Ga0.8As選擇性閘極蝕刻製程
Selective Etch for Gate Recess Process of GaAs/Al0.2Ga0.8As for Low Voltage Power pHEMTs
Authors: 鍾炤正
Chao-Cheng Chung
張 翼
Edward Y. Chang
C.T. Kuo
Keywords: 高電子遷移率電晶體;閘極蝕刻;HEMT(High Electron Mobility Transistor);Gate Recess
Issue Date: 1998
Abstract: 閘極蝕刻法在三-五族半導體元件製程中為一關鍵製程。選擇性閘極蝕刻利用不同材料蝕刻速率的差異,來達到蝕刻深度之控制及均勻性,使三-五族半導體元件製程易於控制。在本論文中以不同的閘極蝕刻溶液來研究其蝕刻特性,利用所發展出的蝕刻溶液來製作假晶高電子遷移率電晶體以證明其可行性。而以SEM及EDX來檢測介面結構,DC I-V 特性及RF特性分別以Tek370,HP4145及Load-Pull 系統來量測,由結果可得到下列結論。 在濃度為0.5M的檸檬酸及0.5M的檸檬酸鉀與30%的雙氧水以5:5:1.5比率混合,pH=5.5的溶液下,此蝕刻溶液對於砷化鎵的蝕刻速率約為40.8 A/秒,而對砷化鋁鎵的蝕刻速率約為0.012 A/秒,即對於砷化鎵/砷化鋁鎵的蝕刻選擇性可以高達3400。因此可減少一般在製程進行時需要反覆地蝕刻與量測飽和電流的次數,而利用此選擇性蝕刻之結果,嘗試應用於假晶高電子遷移率電晶體的閘極蝕刻製程中,不但簡化製程步驟且可避免過度蝕刻之現象。此蝕刻結果可應用於砷化鎵/砷化鋁鎵假晶高電遷移率電晶體閘極蝕刻製程中。
Gate recess is a critical processees in Ⅲ-Ⅴ compound semiconductor device fabrication. In this work, control of the gate recess depth is important in the GaAs device fabrication. Selective etch for gate recess were developed. The pseudomorphic High Electron Mobility Transistor (pHEMT) devices were also fabricated by using the developed etching solution to prove its feasibility. The interface structures were examined by SEM and EDX. The I-V characteristic and RF performance were measured by Tek 370, HP4145 and Load-Pull system, respectively. From the experimental results, the following conclusions can be drawn. At the compositions of [0.5M C6H8O7·H2O]:[0.5M K3H5O7·H2O]:[30% H2O2]= 5:5:1.5 and pH=5.5, the average etching rates are approximately 40.8 A/sec and 0.012 A/sec for GaAs and Al0.2Ga0.8As, respectively, i.e. a selectivity of 3400 was obtained. The etchant was successfully applied to the gate recess for fabricating of GaAs/AlGaAs hetero structure pHEMTs. And devices fabricated show good device performance and uniformity.
Appears in Collections:Thesis