Title: A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion
Authors: Chen, Chia-Pei
Yang, Ming-Jen
Huang, Hsun-Hsiu
Chiang, Tung-Ying
Chen, Jheng-Liang
Chen, Ming-Chieh
Wen, Kuei-Ann
Department of Electronics Engineering and Institute of Electronics
Keywords: Complex bandpass filter;demodulator;frequency synthesizer;low-noise amplifier (LNA);open-loop VCO modulation;time-to-digital converter (TDC)
Issue Date: 1-Dec-2009
Abstract: A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm(2) chip by a 0.18-mu m CMOS process. The receiver achieves -89-dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply.
URI: http://dx.doi.org/10.1109/TCSI.2009.2016184
ISSN: 1549-8328
DOI: 10.1109/TCSI.2009.2016184
Volume: 56
Issue: 12
Begin Page: 2738
End Page: 2748
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