標題: IEEE 802.11n無線區域網路系統之偵測與Viterbi解碼:設計及實現
Detection and Viterbi Decoding for IEEE 802.11n Wireless LAN System – Design and Implementation
作者: 蔡耀毅
Yao-Yi Tsai
吳文榕
Wen-Rong Wu
電機學院電信學程
關鍵字: 多輸入多輸出;正交分頻多工;偵測;維特比;解碼器;設計及實現;IEEE 802.11n;baseband;MIMO;detection;decoding;FPGA;design;implementation;receiver;Viterbi;BICM;OFDM;ZF;MMSE;radix-4;CSI
公開日期: 2005
摘要: 在本論文中,我們考慮IEEE 802.11n基頻接收機之設計與實現。明確地,我們著重在信號偵測與Viterbi解碼。802.11n系統為一個bit-interleaved coded modulation (BICM),多輸入多輸出(Multi-input Multi-output,MIMO)以及正交分頻多工技術(Orthogonal Frequency Division Multiplexing, OFDM)的系統。雖然有許多偵測與解碼演算法是眾所周知的,有效的BICM MIMO-OFDM系統之實現仍舊是一大挑戰。這是因為使用MIMO的結構顯著地增加系統的吞吐量以及在位元串流(bit streams)間引進干擾。模擬顯示Viterbi解碼器前面串接ZF演算法以及其前面串接最小均方差(minimum mean square,MMSE)演算法有著相近的效能。而ZF演算法的計算複雜度較低。因此我們提出使用zero-forcing (ZF)演算法來做信號偵測,而使用Radix-4之trace-back的Viterbi解碼器來做解碼。我們亦提出可以避免ZF演算法以及channel state information (CSI)計算中的除法運算之演算法。使用IEEE預先定義好的通道模型,我們引導出一些模擬結果來評估系統的效能。最後,我們使用FPGA設計流程來實現這個基頻接收機。
In this thesis, we consider design and implementation of an IEEE 802.11n baseband receiver. Specifically, we focus on signal detection and Viterbi decoding. The 802.11n system is known to be a bit-interleaved coded modulation (BICM), multi-input multi-output (MIMO), and frequency division multiplexing (OFDM) system. Although many detection and decoding algorithms are well-known, efficient implementation for the BICM MIMO-OFDM system remains challenging. This is due to the use of the MIMO configuration significantly increasing the system throughput and introducing interference between bit streams. It is shown that the Viterbi decoder pre-cascaded with the ZF algorithm has similar performance with that pre-cascaded with the minimum mean square (MMSE) algorithm. However, the computational complexity of the ZF algorithm is much lower. We thus propose to use the zero-forcing (ZF) algorithm for signal detection and a radix-4 trace-back Viterbi decoder for decoding. We also propose algorithms that can avoid division operations required in the ZF algorithm and channel state information (CSI) calculation. Using IEEE pre-defined channels, we conduct simulations to evaluate the performance of the system. Finally, we implement the baseband receiver with the FPGA design flow.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009167551
http://hdl.handle.net/11536/63691
Appears in Collections:Thesis


Files in This Item:

  1. 755101.pdf