標題: Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
作者: Wu, Meng-Chen
Lu, Ming-Ching
Chen, Hung-Ming
Jou, Jing-Yang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Algorithms;Design
公開日期: 1-十二月-2009
摘要: Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this article, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and can simultaneously consider the tradeoff between power routing cost and total power dissipation.
URI: http://dx.doi.org/10.1145/1640457.1640460
http://hdl.handle.net/11536/6365
ISSN: 1084-4309
DOI: 10.1145/1640457.1640460
期刊: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
Volume: 15
Issue: 1
結束頁: 
顯示於類別:期刊論文


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  1. 000273323600003.pdf