標題: A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation
作者: Chen, MJ
Ho, JS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: back-gate bias;CAD model;CMOS analog circuits;mismatch;subthreshold;process variation
公開日期: 1-四月-1997
摘要: In this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold CMOS analog circuits and systems, This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three, A transparent relationship between the fitting parameters and the process parameters has been derived, and its correlation with a recently widely used CAD model as well as with a well-known two-parameter model has been established, Our extensive measurement work on n-channel MOSFET's has highlighted the potential of the model in handling the variations in the subthreshold I-V characteristics at different back-gate biases arising from process variations, The mismatch analysis has further been successfully performed with emphasis on the reverse back-gate bias effect. In summary, the proposed model can serve as a promising alternative in the area of VLSI subthreshold CMOS analog circuit simulation.
URI: http://dx.doi.org/10.1109/43.602471
http://hdl.handle.net/11536/634
ISSN: 0278-0070
DOI: 10.1109/43.602471
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 16
Issue: 4
起始頁: 343
結束頁: 352
顯示於類別:期刊論文


文件中的檔案:

  1. A1997XM96800002.pdf