標題: 802.11a CMOS頻率合成器設計
Design of CMOS RF Synthesizer for 802.11a
作者: 潘宏良
溫瓌岸
電機學院電子與光電學程
關鍵字: 頻率合成器;鎖相迴路;電壓控制振盪電路;L-C tank電壓控制振盪電路;相位偵測電路;電荷幫浦電路;低通濾波電路;除頻電路;雙頻頻率合成器;相位雜訊;整數型;快速源極耦合邏輯電路;頻率倍頻器;frequency synthesizer;PLL;VCO;L-C tank VCO;phase detector;charge pump;low pass filter;divider;dual mode frequency synthesizer;phase noise;Integer-N;SCL;frequency doubler
公開日期: 2003
摘要: 現今熱門的射頻電路有無數學者在研究,瀏覽各式的論文雖然已成功地在CMOS製程下將VCO特性設計得符合無線網路的規格,但射頻電路容易受干擾的特性若要成功地整合有數位電路的頻率合成器為一顆單晶片,這更是個艱難深入的研究。 本論文是以UMC 0.18μm 1P6M CMOS製程來製作IEEE802.11a WLAN 5GHz U-NII的頻率合成器。晶片採用20腳QFN封裝和使用RO4003材質電路板量測訊號。為了得到低的相位雜訊使用了L-C tank電壓控制振盪電路架構,為了防止製程和溫度的變化並加入開關電容網路電路(SWITCHED-CAPACITOR NETWORK)來增加頻率的振盪範圍,經測試所得可到為22%,和-88.87dBc/Hz@100KHz的相位雜訊(PHASE NOISE),而達輸出頻率為3421MHz∼4177MHz,此外電路還包括,參考頻率電路、相位偵測電路、、低通濾波電路和除頻電路,這些都是經過測試可以正常工作的電路。 為了將電壓控制振盪器的輸出頻率降到和參考頻率一樣,在此篇論文使用整數型(Integer-N)架構以獲得所需要的載波頻率,經過測試後可以選擇載波頻率,且相位頻率鎖住時間為145.0uS。此篇論文也提出802.11b WLAN的2.4GHz配合802.11a WLAN組成雙頻頻率合成器,並經過AGILENT ADS電路模擬。
The radio frequency circuit of nowadays attract lots of researches hot subject that countless scholars wants to develop, various types of thesis made under the very challenge CMOS process had succeed to have VCO characteristic fit the wireless network specification. However, it is a hard study if you would like the easy interfered radio frequency circuit combine successfully with digital cirtcuit frequency synthesizer to a single of chip. The design is fabricated in UMC 0.18um 1P6M CMOS process to make frequency synthesizer, according to IEEE802.11a WLAN of 5GHz U-NII specification. The chip adopts 20 pin QFN package and uses RO4003 substrate circuit's board examine the signal. Usign L-C tank VCO structure of the circuit in order to get the low phase noise and prevent temperature and process variations, we added switched capacity network circuit to increase frequency tunning range. After examining, the tunning range is 22%, and phase noise is -88.87dBc/Hz@100KHz, and outputs frequency is 3421MHz- 4177MHz. In addition the circuit also includes reference frequency circuit, phase detect circuit, charge pump circuit, low pass filter circuit and frequency divider circuit. All these circuits can function work normally through measurements. In order to make the output frequency of the VCO as low as reference frequency, we use the structure of the integer-N divider to get carrier frequency in this thesis. The integer-N divider can choose channel frequency and the phase settling time is 145uS after testing. This thesis also proposes dual mode frequency synthesizer based on 802.11a WLAN structure that can be adapted to 2.4GHz 802.11b WLAN.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009167512
http://hdl.handle.net/11536/63379
Appears in Collections:Thesis


Files in This Item:

  1. 751201.pdf
  2. 751202.pdf