標題: 電漿充電所產生氧化層可靠問題及P-快閃記憶元件之設計方法
Oxide Reliability Issues Caused by Plasma Charging and Design Methodology for P-flash Memory
作者: 游國豐
You, Kuo-Feng
Ching-Yuan Wu
關鍵字: 電漿;Plasma
公開日期: 1997
摘要: 本論文廣泛且徹底地探討電漿製程引發的閘氧化層破壞效應,以及其 對積體電路製造的衝擊。藉由本論文發展的模擬器,可以精準模擬出半導 體元件在電漿製程中的充放電行為,並且準確預測閘氧化層的傷害程度。 另外,本文亦提出一些有效的解決方法以減輕電漿製程所造成的破壞。再 者,為了正確計算能帶穿透電流,本文提出二維熱載子能帶穿透電流模型 ,依此模型可以輕易地設計低漏電流,高寫入電流的高效能P型快閃記憶 體。 第一章概述電漿充電傷害對快閃記憶體的影響,以及發展二維熱 載子能帶穿透電流模型的重要性並簡述本論文的組織架構。 第二章提 出一個可診斷互補金氧半技術中每一不同電漿製程所造成傷害程度的方法 ,並展示電漿傷害與天線比率及導線周長的關係。最後設計一些保護界面 來減輕電漿傷害。 第三章提出一個新的等效電路模型用來模擬薄閘氧 化層在電漿灰化製程中的傷害程度。本模型考慮差分電容、基片寄生電阻 、平帶電壓、以及在電漿製程中產生介面能階╱氧化層陷阱所引起的回饋 效應。依此模型計算出的閘極電流與量測出的隱介面能階俱有高度相關, 因此可用來預估介面能階╱氧化層陷阱密度與天線比率的關係,以提供電 路設計準則。此外,本章亦探討電漿離子濃度、電漿均勻度、薄氧化層厚 度以及基片摻入雜質濃度與電漿傷害的關係。 在第四章中,我們提出 一個先用活化離子蝕刻,再用濕性蝕刻的二階段蝕刻方法來減輕電漿傷害 。在比較用此方法與用傳統純活化離子蝕刻複晶矽閘,發現其下之氧化層 在經過時間相關介電質崩潰、高頻電容電壓、低頻電容電壓等測試後,電 漿傷害已大幅減輕。因此本方法可提高閘氧化層的良率,並可用於互補金 氧半技術中,以取代純活化離子蝕刻製程。 在比較現有的一維或二維 能帶穿透電流模型所模擬閘極引發汲極漏電流與量測的結果後,發現極顯 著不符。閘極引發汲極漏電流顯然不僅和汲極與閘極重疊區域的垂直電場 有關,且與水平電場亦相關。因此在第五章提出汲極引發能障縮減的二維 熱載子能帶穿透電流模型。由於本模型同時考慮垂直和水平電場,因此模 擬出的結果與量測的結果在大閘極汲極電壓變動下亦極為符合。依此模型 ,可準確預估閘極引發汲極漏電流,並可作一些實際應用。 最後,在 第六章中,將本論文之重要貢獻做一整理回顧並做一總結,且展望值得延 伸探討的研究方向。 Plasma-induced oxide damage (PIOD) is studied extensively and thoroughly inthis thesis. The impacts on the modern integrated circuit (IC) fabrication arepresented. The behaviors of the charging effect are simulated in our developedsimulator and the solutions for preventing from the plasma etching damage is also proposed. Moreover, for exactly calculating the band-to-band tunnelingcurrent, a quasi-2D model for hot-carrier band-to-band tunneling current is proposed in this thesis. Based on this model, the excellent performance of flash memory, including lower OFF-state current and the high programmingcurrent, can be easily achieved. In Chapter 1, the impacts and importance of the plasma charging damage onflash memory are introduced. The reason which develops a new quasi-2D band-to-band tunneling model is described and the organization of the thesisis given. In Chapter 2, the methodology of discriminating the damage caused by eachstep of complementary metal-oxide-silicon (CMOS) technology is designed. Moreover, the relationship between antenna ratios/peripheral length of conductor and the plasma damage are shown. Eventually, several special structures are laid out to prevent the plasma damage. In Chapter 3, to simulate thin gate-oxide damage due to plasma ashingprocess, a new equivalent circuit model is proposed by including a differentialcapacitance, a parasitic resistance, an offset flatband voltage, and the effects of feedback on the interface- state and trapped oxide charge densitiesgenerated during plasma ashing process. According to this new model, computation of gate oxide charging current is performed by correlating to thelatent interface-state density. The test n-MOSFET devices, including differentantenna-ratios are measured, and excellent agreement is obtained as comparedwith measured results. Therefore, the relationships between interface states/oxide traps and antenna ratio are linked to provide a guideline for circuitdesigners and the plasma ashing process-induced damage can be predicted. Moreover, the effects of plasma ion density, plasma uniformity, thin gate-oxidethickness and substrate doping concentration on plasma-induced oxide damages are investigated by the developed physical model. In Chapter 4, a novel two-step etching process using reactive ion etching(RIE) following wet etching is proposed to reduce the gate oxide chargingcurrent. The characteristics of the proposed process for gate oxide protectionare characterized by time-dependent dielectric breakdown (TDDB), high-frequencycapacitance-voltage (HFCV), and quasi-static capacitance-voltage (QSCV)measurements. From measurement results, it is shown that degradation of the gate oxide is dramatically eliminated by the proposed two-step etching methodas compared with that using pure RIE. Therefore, the proposed two-step etchingprocess can replace the pure dry etching process to reduce the plasma-inducedgate oxide damage. A significant mismatch occurs when we predict the gate-induced drain leakagecurrent (GIDL) by using all existing 1D and 2D models. It was found that the gate-induced drain leakage current is attributed to not only the verticalfield but also the lateral field near the drain-to-gate overlap region. Therefore, in Chapter 5, a new quasi-2D model considering both the lateral andvertical fields for predicting the gate-induced drain leakage current is proposed by using the drain-induced energy-barrier reduction in our model. Thecalculated results using the developed quasi-2D model are in good agreement with measured values for a wide range of gate and drain biases and gate oxidethicknesses. Therefore, the proposed new model can be used to predict the band-to-band tunneling current for practical applications. Finally, conclusions are given in Chapter 6. Important researches are proposed as the future works.
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