標題: DC and RF Performance Improvement of 70 nm Quantum Well Field Effect Transistor by Narrowing Source-Drain Spacing Technology
作者: Kuo, Chien-I
Hsu, Heng-Tung
Chang, Edward Yi
Miyamoto, Yasuyuki
Wu, Chien-Ying
Chen, Yu-Lin
Hsiao, Yu-Lin
材料科學與工程學系
Department of Materials Science and Engineering
公開日期: 2010
摘要: A 70 nm InAs channel quantum well field effect transistor (QWFET) fabricated by a narrowing source-drain (S/D) spacing technique was realized for future high-speed and logic applications. The S/D spacing was decreased from 3 to 0.65 mu m through a simple fabrication process, which is an ameliorative redeposition ohmic technique. The drain-source current density and transconductance of the device were increased from 391 to 517 mA/mm and from 946 to 1348 mS/mm after the scaling of the S/D spacing, respectively. In addition, the current gain cutoff frequency (f(T)) was also increased from 185 to 205 GHz. These results show that the easy method can effectively improve the III-V QWFET device performance for high-frequency and high-speed applications. (C) 2010 The Japan Society of Applied Physics
URI: http://hdl.handle.net/11536/6278
http://dx.doi.org/10.1143/JJAP.49.010212
ISSN: 0021-4922
DOI: 10.1143/JJAP.49.010212
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS
Volume: 49
Issue: 1
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