標題: 用於移動估測之記憶體組織與其界面
Memory Organization and Its Interface to PEs for Motion Estimation
作者: 段人傑
Tuan, Jen-Chien
任建葳
Je, Chein-Wei
電子研究所
關鍵字: 移動估測;記憶體
公開日期: 1996
摘要: 移動估測是目前動態影像壓縮過程中經常使用到的一項技術。其目的是為了要善加利用存在於動態影像中,短時間內前後幾張畫面所呈現的高度相關性,將之納入編碼時的考量,如此可大幅降低在動態影像編碼結果中所需要的儲存空間或是傳輸頻寬。而這項移動估測的技術本質上乃一連串比較的步驟,比較前後畫面在什麼位置最相似,這個步驟需要大量1的資料流量,目前的技術下不可能以直觀的方式加以實作,利用內建記憶體的設置來降低所需要的資料流量是常用的解決方法。而這也帶來內建記憶體要如何配置、如何與計算單元連結及需要多少的內建記憶體等問題。本論文的主旨即在研究這些與內建記憶體設置的相關問題。 在論文中首先簡介移動估測的理論背景,以及許多研究者所提出的移動估測演算法,並對過去提出的實作架構作簡短的介紹。接著說明在移動估測技術下之所以會消耗大量資料流量的原因,研究移動估測演算法下所展現的資料重覆使用的特性,這種特性可以被利用來降低資料流量,代價是需要內建記憶體的設置。文中對此重覆利用特性作程度分類,在不同程度下需要不同數量的記憶體,而對資料流量的降低也有不同的效果,記憶體的組織也會對其與計算單元的界面有所影響。文中對現有架構的記憶體組織與數量做了分析。最後根據所做分析提出一架構,此架構對資料流量的降低效果顯著,並在記憶體的組織與數量上亦有近於理論值的表現。
In motion pictures compression process, motion estimation is a widely used technique. Motion estimation is adopted to explot the temporal redundancy existed among successive frames in a motion picture sequence. By utilizing this temporal redundancy, the storage capacity and transmission bandwitdth can be reduced. Along with this motion estimation technique, requirement of huge frame memory bandwidth is introduced. The amount of bandwidth is beyond the current technique can afford. The set up of on chip memory can effectively deal with this problem. The size of on chip memory, organization of the on chip memory and its interface to PEs have to be carefully considered. These are discussed in this dissertation. First the basis of motion estimation is described. Various search algorithms and published architectures for motion estimation are also discussed briefly. Then the reason why motion estimation process consumes huge bandwidth is explained. Property of data reuse is analyzed. Such property can be used to reduce the required frame memory bandwidth by the cost of on chip memory. Under different degrees of data reuse, the required on chip memory size differs. Analysis of on chip memory organization and its interface to PEs are applied to presented architectures. According to our analysis, a high efficiency architecture which meets the minimum memory bandwidth is proposed.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT853430002
http://hdl.handle.net/11536/62337
Appears in Collections:Thesis