標題: 串接式交換電容濾波器之系統化設計
Systematic Dsign Mthodology for Cscaded SCF Crcuit
作者: 甯中和
Ning, Chung-Ho
溫壞岸
Kuei-Ann Wen
電子研究所
關鍵字: 交換電容濾波器;串接式;switched-capacitor-filter;cascaded
公開日期: 1996
摘要: 串接式交換電容濾波器之系統化設計 研究生:甯中和 指導教授: 溫壞岸國立交通大學電子工程學系 電子研究所碩士班摘要 由於交換 電容濾波器具高度精確的積體電路實現能力,所以已廣泛的作為通訊和混 合式數位類比積體電路的重要架構單元,本篇論文提出串接式交換電容濾 波器在時間、頻率、和z領域的系統化設計分析方法;此種方法能提供穩定 的z領域轉換函數、較小的參數變化的敏感度、較小的總電容值、較大對 雜散電容的免疫力和最大的動態範圍(dynamic range).我們也提出了新的 二階架構方法和選擇依據準則以降低串接式交換電容濾波器之最大最小電 容分佈比。 我們設計了一個經由輸入一些限制條件和規格,就能簡易 分析及合成串接式交換電容濾波器的程式,它能自動產生SWITCAP軟體的輸 入格式檔案,以便作更進一步的模擬和驗證,此外它亦能產生佈局所需的重 要資訊;若我們使用此程式,則能在很短的時間內有效率的設計串接式交換 電容濾波器。 此系統化設計分析方法已經由兩個設計實例加以驗證,其 中一個是單音複頻接收器,另一個是FSK解碼器;這兩個設計實例,都已用互 補式金氧半電晶體1.2um雙層多晶矽單層金屬製程加以實現。 Systematic Design Methodology for Cascaded SCF CircuitStudent: Chung-Ho Ning Adviser: Kuei-Ann Wen Institute of Electronics National Chiao-Tung University Abstract Switched capacitor filter (SCF) has been widely used as an important building block in telecommunication and mixed-mode circuit applications for its highly precision monolithic implementation ability. This thesis would present systematic analysis methods and design methodologies for cascaded SCF circuit in the time, frequency, and z-domain. The design methodologies could provide stable z- domain transfer function, small sensitivities to parameter value variation, small total capacitance, insensitivity to parasitic capacitance, and maximum dynamic range. We also present some new biquad configuration methods and biquad selection criteria for lower capacitor spread in cascaded SCF. We design a useful program that could analysis and synthesis cascaded SCF circuit easily by entry of some restrictions and desired specifications. It could also automatically generate input files for SWITCAP for further simulation and verification. Moreover, it also provides some important information for layout. Using this program, we could easily design a cascaded SCF more efficiently during a short time. The design methodologies have been proved successfully by two design examples. One is used in DTMF receiver. Another design is to implement an FSK decoder. The two designs all have been implement with a 1.2um double poly single metal CMOS technology.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT850428142
http://hdl.handle.net/11536/62020
Appears in Collections:Thesis