Title: High Performance of Ge nMOSFETs Using SiO(2) Interfacial Layer and TiLaO Gate Dielectric
Authors: Chen, W. B.
Chin, Albert
Department of Electronics Engineering and Institute of Electronics
Issue Date: 1-Jan-2010
Abstract: Using a SiO(2) interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO(2) on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.
URI: http://dx.doi.org/10.1109/LED.2009.2035719
ISSN: 0741-3106
DOI: 10.1109/LED.2009.2035719
Volume: 31
Issue: 1
Begin Page: 80
End Page: 82
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