標題: Discrete-Dopant-Induced Power-Delay Characteristic Fluctuation in 16 nm Complementary Metal-Oxide-Semiconductor with High Dielectric Constant Material
作者: Han, Ming-Hung
Li, Yiming
Hwang, Chih-Hong
傳播研究所
電機工程學系
Institute of Communication Studies
Department of Electrical and Computer Engineering
公開日期: 2010
摘要: In this work, we carry out an experimental validated three-dimensional "atomistic'' device-circuit coupled simulation to study the discrete-dopant-induced power and delay fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits. The equivalent gate oxide thicknesses (EOTs) of planar CMOS range from 1.2 nm to 0.2 nm. SiO(2) is used at gate oxide thicknesses of 1.2 and 0.8 nm, Al(2)O(3) at an EOT of 0.4 nm, and HfO(2) at an EOT of 0.2 nm. Under the same device threshold voltage, as EOT decreases from 1.2 to 0.2 nm, the fluctuations of threshold voltage and gate capacitance for CMOS transistors are reduced by 43 and 55%, respectively. For the state-of-art nanoscale circuits using high-dielectric constant (high-kappa) materials, the delay time fluctuation is suppressed significantly from 0.1 to 0.03 ps. For the power characteristics, although the nominal powers of circuits using high-kappa dielectrics are increased owing to the increased EOT, the fluctuations of dynamic power, short circuit power, and static power are reduced by 40, 70, and 30%, respectively. (C) 2010 The Japan Society of Applied Physics
URI: http://hdl.handle.net/11536/6036
http://dx.doi.org/10.1143/JJAP.49.04DC02
ISSN: 0021-4922
DOI: 10.1143/JJAP.49.04DC02
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS
Volume: 49
Issue: 4
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