Title: A new simulation model for plasma ashing process-induced oxide degradation in MOSFET
Authors: You, KF
Chang, MC
Wu, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Issue Date: 1-Jan-1998
Abstract: Plasma ashing process-induced oxide damage is studied quantitatively in this paper, To simulate thin gate-oxide damage due to plasma ashing process, a new equivalent circuit model is proposed by including a differential capacitance, a parasitic resistance, an offset flatband voltage, and the effects of feedback on the interface-state and trapped oxide charge densities generated during plasma ashing process, According to this new model, computation of gate oxide charging current is performed by correlating to the latent interface-state density, The test n-MOSFET devices including different antenna-ratios are measured, and excellent agreement is obtained as compared with measured results, Moreover, the deficiency of the previous model is stated and compared, In addition, the effects of substrate doping concentration on plasma-induced oxide damage are also investigated as well as those of plasma ion density, plasma uniformity, thin gate-oxide thickness, Therefore, the relationships between interface state/oxide traps and antenna ratio are linked to provide a guideline for circuit designers and the plasma ashing process-induced damage can be predicted.
URI: http://dx.doi.org/10.1109/16.658837
http://hdl.handle.net/11536/60
ISSN: 0018-9383
DOI: 10.1109/16.658837
Journal: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 45
Issue: 1
Begin Page: 239
End Page: 246
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