標題: New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS
作者: Chen, Wen-Yi
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electrostatic discharge (ESD);lateral DMOS (LDMOS);open drain
公開日期: 1-二月-2010
摘要: In high-voltage applications, large-array n-channel lateral DMOS (LA-nLDMOS) is usually required to provide high driving capability. However, without following the foundry-suggested electrostatic discharge (ESD) design guidelines in order to reduce total layout area, LA-nLDMOS is easily damaged once the parasitic bipolar junction transistor is triggered under ESD stresses. Accordingly, the bipolar triggering of LA-nLDMOS usually limits the ESD robustness of LA-nLDMOS, particularly in the open-drain structure. In this letter, a new layout arrangement for LA-nLDMOS has been proposed to suppress the bipolar triggering under ESD stresses. Measurement results in a 0.5-mu m 16-V bipolar CMOS DMOS process have confirmed that the new proposed layout arrangement can successfully increase the human-body-model ESD level of the LA-nLDMOS with effective width of 3000 mu m from the original 0.75 kV up to 2.75 kV.
URI: http://dx.doi.org/10.1109/LED.2009.2037343
http://hdl.handle.net/11536/5939
ISSN: 0741-3106
DOI: 10.1109/LED.2009.2037343
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 31
Issue: 2
起始頁: 159
結束頁: 161
顯示於類別:期刊論文


文件中的檔案:

  1. 000274018000023.pdf