標題: A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
作者: Lin, Yi-Min
Chen, Chih-Lung
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Bose-Chaudhuri-Hochquenghem (BCH) codes;digital video broadcasting;DVB-S2;error-correction coding
公開日期: 1-十一月-2010
摘要: This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Bjorck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.
URI: http://dx.doi.org/10.1109/JSSC.2010.2065630
http://hdl.handle.net/11536/5901
ISSN: 0018-9200
DOI: 10.1109/JSSC.2010.2065630
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 45
Issue: 11
起始頁: 2330
結束頁: 2340
顯示於類別:會議論文


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