標題: A novel modeling technique for efficiently computing 3-D capacitances of VLSI multilevel interconnections BFEM
作者: Hou, HM
Sheen, CS
Wu, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: BFEM;Green's function;interconnection;3-D capacitance;VLSI
公開日期: 1-一月-1998
摘要: An efficient method is presented to model the parasitic three-dimensional (3-D) capacitance of VLSI multilevel interconnections. Based on the boundary-finite-element method (BFEM) of integral formulation, arbitrary triangle elements on the surface of conductors for charge distribution are used to efficiently calculate capacitances of both parallel conductors and complicated configurations such as crossing Lines, corners, contacts, and their combinations, Using an adaptive multilevel Green's function and low-order polynomials as shape function, we apply the Galerkin principle over finite elements, and most of the surface integrals of charge distribution can be evaluated analytically and the singular integrals can be eliminated by choosing proper coordinate transformation, Moreover, an even less complex and more general method for arbitrary geometry configuration of multilevel interconnection lines is proposed in order to Link with the finite element pre-processor in present CAD tools.
URI: http://dx.doi.org/10.1109/16.658831
http://hdl.handle.net/11536/59
ISSN: 0018-9383
DOI: 10.1109/16.658831
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 45
Issue: 1
起始頁: 200
結束頁: 205
顯示於類別:期刊論文


文件中的檔案:

  1. 000071225200027.pdf