標題: Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications
作者: Hsu, Li-Han
Wu, Wei-Cheng
Chang, Edward Yi
Zirath, Herbert
Wu, Yun-Chi
Wang, Chin-Te
Lee, Ching-Ting
材料科學與工程學系
電子工程學系及電子研究所
Department of Materials Science and Engineering
Department of Electronics Engineering and Institute of Electronics
關鍵字: Fabrication;interconnections;microelectromechanical devices;microwave technology;packaging
公開日期: 1-Feb-2010
摘要: This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.
URI: http://dx.doi.org/10.1109/TADVP.2009.2034137
http://hdl.handle.net/11536/5893
ISSN: 1521-3323
DOI: 10.1109/TADVP.2009.2034137
期刊: IEEE TRANSACTIONS ON ADVANCED PACKAGING
Volume: 33
Issue: 1
起始頁: 30
結束頁: 36
Appears in Collections:Articles


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