標題: The role of resist for ultrathin gate oxide degradation during O-2 plasma ashing
作者: Chien, CH
Chang, CY
Lin, HC
Chiou, SG
Huang, TY
Chang, TF
Hsien, SK
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-五月-1997
摘要: During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect, Recently, we found instead that resist does not simply act as a protection layer, This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study, In this letter, we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer, The experimental results show a good correlation with our explanation, To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period.
URI: http://dx.doi.org/10.1109/55.568764
http://hdl.handle.net/11536/589
ISSN: 0741-3106
DOI: 10.1109/55.568764
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 18
Issue: 5
起始頁: 203
結束頁: 205
顯示於類別:期刊論文


文件中的檔案:

  1. A1997WU99600012.pdf