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  1. You are Here:National Chiao Tung University Institutional Repository
  2. Publications
  3. Thesis

標題: 數位系統障礙模擬器之研究
Fault simulators of digital system
作者: 吳敬平
Wu, Jing Ping
李崇仁
沈文仁
Li, Chong Ren
Shen, Wen Ren
電子研究所
公開日期: 1993
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT822430010
http://hdl.handle.net/11536/58522
Appears in Collections:Thesis


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  • 數位電路之延遲測試與障礙模擬 / 吳文慶;Wu, Wen Ching;李崇仁;Chung Len Lee
  • A two-phase fault simulation scheme for sequential circuits / Wu, WC;Lee, CL;Chen, JE
  • EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATOR / JOU, SJ;CHIOU, SH;TAO, YS;SHEN, WZ
  • DISTRIBUTED FAULT SIMULATION FOR SEQUENTIAL-CIRCUITS BY PATTERN PARTITIONING / WU, WC;LEE, CL;CHEN, JE;LIN, WY
  • 一個測試圖樣平行障礙平行序向邏輯電路障礙模擬硬體加速器 / 謝宗宏;Tzong-Honge Shieh;李崇仁;Chung-Len Lee
  • A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits / Hong, Hao-Chiao
  • Detection and Identification of Actuator Faults in Robotic Systems Based on Multiple-Model Nonlinear State Estimation / Hsiao, Tesheng;Haung, Huei-jyun
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