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dc.contributor.authorJuinn-Kuo Tsoen_US
dc.contributor.authorKuei-Ann Wenen_US
dc.description.abstract在本論文中,跟據MPEG之解碼要求我們設計了:變動長度解碼器,長度解碼 器,逆向量化器,逆向數位餘弦轉換器.而變動長度解碼器以一個平行式解 碼器為基礎,它可於一個時鐘週期中解任意長度的碼,完成此架構只需些 PLA,計數器,暫存器及一些隨機羅級閘.對於長度解碼器,逆向量化器為了 適合在硬體上實現也採用規則之RAM,PLA來設計.至於逆向數位餘弦轉換器 採用分散式數學之方法,所以不須要任何之乘法器,只須些暫存器,ROM,及 加法器來完成,此架構具有相當之規則性,非常適合VLSI之製作.對於圖像 處理器,我們採用讀寫交替之方式以及分割計憶體為多個庫來解決顯示上 及移動補償須同時取用計憶體之問體.我們以0.8um COMS之技術來實現長 度解碼器,逆向量化器,數位餘弦轉換器,其面積分別為2543.4umX2593.2 um, 2897.3umX3435.3um, 4530.5umX6515.4um. In our design, the modulized approach was used and in order to match the MPEG decoding requirement, we designed some function unit:VLD, RLD, inverse quantizer,inverse DCT and frame processor. The architecture of the VLD is based on a parrel structure deco- der.It can decode a codeword within one clock cycle regardless of its length. This unit needs only PLA, counter,adder and some random logic. For RLD and inverse quantizer, from the aspect of hardware implementation, we also use the regular structure, such as PLA and RAM, to design the architecture. We use the distrib- uted arithmetic to design the architecture of the inverse DCT function unit. In this unit, there is no multipliers, We only used registers, ROM and adder to implement it. This architecture is very regular and is suited for VLSI implementation. For the frame processor, we adopt reading operation and writing operation interleaving and divided the frame memory into some memory banks to solve the problem that the display and motion compensation need to access the memory at the same time. We used 0.8 um CMOS technology to design RLD, inverse quantizer and inverse DCT. The area of the RLD, inverse quantizer and inverse DCT is 2543.4umX 2593.2um,2897.3umX3425.3um and 4530.5umX6514.4um,respectly.zh_TW
dc.subjectVariable length decoder;run length decoder;inverse quantizer; inverse discrete cosine transform;en_US
dc.titleMPEG-I 視訊解碼器之設計zh_TW
dc.titleDesign of MPEG-I Video Decoderen_US
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