標題: 多媒體系統晶片平台的設計與應用
Design and Application of Multimedia System-on-Chip Platform
作者: 鍾仁峰
Jen-Feng Chung
林進燈
Chin-Teng Lin
電控工程研究所
關鍵字: 數位訊號處理器;增強式系統匯流排;三度空間立體音效;可規化的邏輯陣列元件;空間迴響器;嵌入式;線性估測編碼;音高估測;DSP;AMBA;3-D sound;FPGA;Reverberator;Embedded;LPC;Pitch Estimation
公開日期: 2005
摘要: 多媒體訊號處理涵蓋兩大核心領域,一為影像及視訊處理,另一為語音及音效處理。它的應用適合於家庭娛樂系統中及資訊科技產業,具體的產品包括寬頻網路影音系統、數位廣播系統、多聲道視聽系統、及高音質隨身音樂媒體等。這些系統為了滿足人類聽覺的需要,即時運算是必須的。然而,多媒體處理計算的需求是由訊號處理的工作分配,若執行高的取樣頻率也就是處理較大的資料量,則需要複雜運算。以多媒體的角度而言,它必須處理多不同類型的數據,但使得處理的工作變得複雜化。本論文針對特別利用在語音與音訊處理上的計算特性,開發出一種新型的多媒體處理的架構來解決快速驗證平台的問題。 多媒體系統晶片平台的開發以聲音為導向,針對消費性3C產品做整合性的開發設計,它不僅適用多聲道音源輸入與不同喇叭或耳機輸出都可以增強音效的SoC雛型設計環境,以便對所需求的規格來確定主系統的架構。在這個規劃中我們提出了三階段的週期:系統規劃週期、系統設計週期、及系統驗證週期。多媒體系統處理核心為模組控制,模組控制就像是一個軟體的智財 (IP) 插座,可以透過相同的電子設計自動化 (EDA) 平台環境進行整合,以微處理器來分配系統資源,提供數位訊號處理器執行所需的功能。系統匯流排依循AMBA 匯流排的時序設計,並提供IP標準的的介面,充分發揮系統執行的效能。用傳統微處理器和數位訊號處理器的相互搭配架構,是未來數位電子的趨勢,亦是降低硬體成本的考量。 本論文中的多媒體系統晶片平台提出了一個FPGA的設計與驗證方法,系統晶片設計部分包含了系統匯流排、微處理控制器、周邊數位I/O、16位元空間迴響器、及24位元適用於音訊系統之數位訊號處理器等。可程式化微處理控制器負責系統晶片內部的流程處理和周邊I/O控制;24位元數位訊號處理器因其架構與指令集是特別針對音訊系統的主要演算法做考量;16位元空間迴響器則是一個即時3-D音效處理的智財 (IP),這兩個處理器分別並連接於高速及周邊匯流排上。系統晶片驗證部分包含語音線性估測編碼的參數求取、音高位置估測、和空間迴響器等演算法的資料測試與訊號驗證。此平台搭配處理器指令與 gated-clock 的方法,可適應性的調整算數邏輯單元的使用,具有省功率運作的特性,非常適合音訊多媒體系統中可攜式與低功率要求的應用。使用FPGA經過驗證與測試整個系統的執行效能平均達80MIPS,功率消耗在90mW。此設計是跨平台的實現方法,未來可整合到任意單一矽晶片之中。
Multimedia signal processing involves two important fields: one is image and video processing; the other is speech and audio processing. It is suitable to be applied into the system of home entertainment and the industry of information technology, for example, the concrete products such as a wide-band video-audio system of networks, a digital broadcast system, a multi-channel video-audio system, a high-quality walkman, etc. To satisfy the requirement of human hearing, it is necessary for real-time processing. However, the assignment of multimedia signals depends on the requirement of computational power. If a system has to process mass data, i.e., high operating frequency, it should perform complex operations. Because data is composed of different signals in the multimedia world, the work of signal processing becomes complication. In this thesis, we make use of computational characteristics of speech and audio processing and design a new architecture of multimedia processing in order to solve the problem of verification quickly. Based on the conception of sound processing, a multimedia System-on-Chip (SoC) platform, which can integrate 3C consumer products, is designed. It is not only suitable for multi-channel sound input or output such as speakers or headsets, but also achieves the effect of virtual sound. We are in accordance with three phase cycles as specification, design, and verification for assisting the platform design. The kernel of the SoC platform is like a module control. The module control is just like as the software socket of intelligence property (IP). Thus, we can integrate with IPs via the environment of electronic design automation (EDA). In the platform, a microprocessor is as the master to assign system resources. The system bus meets the timing of AMBA and offers the standard AMBA interface to promote performance and to reduce hardware costs. The architecture of traditional microprocessor and digital signal processor (DSP) is the trend of digital circuit design in the future. In this thesis, we present design and verification of the multimedia SoC platform. The platform design integrates the system bus, microprocessor, memory controller, peripheral I/O, 16-bit reverberator, 24-bit DSP, etc. The programmable microprocessor manages internal data flow and digital I/Os. The 24-bit DSP is specified as its architecture and instruction set for sound algorithms. The 16-bit reverberator is 3-D virtual sound IP performed in real time. The two processors are connected to the high-performance bus (AHB) and the peripheral bus (APB), respectively. The platform verification includes the speech parameters of linear predictive coding, pitch estimation, and reverberation. These algorithms are used to test data flows and to verify functionality for the proposed SoC platform. By using the gated-clock scheme, the platform has reducing power characteristics so that it can adaptively adjust the usage of parallel ALUs. Finally, under FPGA verification and testing, on average the whole performance obtains 80MIPS, and power consumption is about 90mW. Due to a cross-platform implemented scheme, it can be applies into an embedded and portable multimedia system and can also be integrated to a single silicon chip.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008812813
http://hdl.handle.net/11536/56556
Appears in Collections:Thesis


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