Title: A 125 mu W, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications
Authors: Liu, Tsu-Ming
Lin, Ting-An
Wang, Sheng-Zen
Lee, Wen-Ping
Yang, Jiun-Yan
Hou, Kang-Cheng
Lee, Chen-Yi
Department of Electronics Engineering and Institute of Electronics
Keywords: H.264/AVC;inverse discrete cosine transform (IDCT);mobile communication;motion compensation;MPEG-2;video coding
Issue Date: 1-Jan-2007
Abstract: A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18 mu m one-poly six=metal CMOS technology with an area of 15.21 mm(2). For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 mu W and 108 mu W, respectively, at 1 V supply voltage.
URI: http://dx.doi.org/10.1109/JSSC.2006.886542
ISSN: 0018-9200
DOI: 10.1109/JSSC.2006.886542
Volume: 42
Issue: 1
Begin Page: 161
End Page: 169
Appears in Collections:Conferences Paper

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