標題: Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks
作者: Hsu, Jenchien
Su, Chauchin
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: Analog testing;built-in self test;jitter;jitter measurement;phase-locked loop (PLL);spread-spectrum clock (SSCs)
公開日期: 1-Apr-2010
摘要: This paper presents a built-in jitter measurement approach for measuring the timing jitter of spread-spectrum clocks (SSCs) and a jitter estimation method for validating the approach. Because of the lack of dedicated measurement instruments for SSC timing jitter measurement, the jitter estimation method is proposed to correlate SSC and non-SSC jitter. A 1.2-GHz eight-phase SSC generator with the jitter measurement circuit is designed and fabricated using the 0.18-mu m complementary metal-oxide semiconductor technology. The measured results are validated by the proposed estimation method, which is the key contribution of this paper. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026 UI.
URI: http://dx.doi.org/10.1109/TIM.2009.2025992
http://hdl.handle.net/11536/5601
ISSN: 0018-9456
DOI: 10.1109/TIM.2009.2025992
期刊: IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Volume: 59
Issue: 4
起始頁: 847
結束頁: 856
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