標題: Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism
作者: Liao, Chia-Chun
Chiang, Tsung-Yu
Lin, Min-Chen
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
關鍵字: Contact etch-stop layer (CESL);poly amorphization implantation (PAI);strain;stress memorization technique (SMT)
公開日期: 1-四月-2010
摘要: In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should bemodulated from the point of view of stress shift rather than using the highest tensile film.
URI: http://dx.doi.org/10.1109/LED.2010.2041524
http://hdl.handle.net/11536/5571
ISSN: 0741-3106
DOI: 10.1109/LED.2010.2041524
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 31
Issue: 4
起始頁: 281
結束頁: 283
顯示於類別:期刊論文


文件中的檔案:

  1. 000276017000008.pdf