In this thesis, the analytic common models for the threshold voltage, the drain current, the substrate current, and the transistor charges of both conventional and LDD MOSFET's have been developed. In chapter 1, we will point out the fact that the LDD structure can reduce the high7 field effects existing in conventional. MOSFET's but the extra parasitic resistance in the LDD structure, which is bias7 controlled, will reduce the transconductance and increase the saturation voltage. A set of test devices with conventional and LDD structures fabricated by ERSO, ITRI, have been measured and characterized. Observing from the features of the common model, the major applications are in circuit7 level analyses and simulations. Besides, the hints for device design can also be obtained by the common models due to their structure/process oriented features. In Chapter 2, the threshold7 voltage models for conventional and LDD MOSFET's have been presented, in which the implanted channel profile is approximated by a step profile, and the short7 channel effect is modeled by combining a charge sharing scheme and the superposition of the bulk depleted charges. Considering the built7 in voltages across the setp junctions, the discontinuities of the threshold voltage have been eliminated. By replacing the heavily doped concentration of the source/drain regions to lightly doped drain doping, the threshold voltages of LDD MOSFET's can be easily calculated. Although the disagreements of the threshold voltage for larger substrate biases can be observed from comparisons between the calculated and measured results. The deficiency is due to the assumption that the surface potential along the channel is constant. However, the developed threshold7 voltage moedls are still applicable for practical substrate biases. In Chapter 3, the drain7 current model for conventional MOSFET's has been derived by considering field7 dependent mobility, short7 channel threshold voltage, implanted channel profile, and constant parasitic resistance. Based on the derivations for conventional MOSFET's and taking the n-region as a buried7 channel MOSFET with a modified charge sharing scheme, the drain7 current model for LDD MOSFET's has been developed. Besides, the drain currents for conventional and LDD MOSFET's operated in the saturation region have been obtained by using one7 dimensional approximation. Using the parameters determined by a series of least7 square fittings, the calculated drain currents have been shown to satisfactorily agree with the measured data. In Chapter 4, the analytic substrate7 current models for conventional and LDD MOSFET's have been developed by using the pseudo two7 dimensional approximation in the channel and drain regions to obtain both the channel length modulation factors and the maximum electric field. By using an existing simplified substrate current formula and the developed mzximum electric field, the substrate currents of conventional/ LDD MOSFET's have been calculated. Besides, the drain current can also be self7 consistently calculated by using the I7 V moedl in Chapter 3 and the developed channel length modulation factor. Using a two7 dimensional numerical MOS device simulator, it has been shown that the accuracy of the developed maximum electric field model is acceptable for calculating the substrate currents of conventional/LDD MOSFET's. Moreover, the parameters used in the substrate7 current models can be determined by the developed optimization technique. Comparing the calculated drain and substrate currents with the experimental data measured. form the test devices with conventional/LDD MOS structures, the developed substrate7 current models have been shown to be valid for wide ranges of channel lengths and bias conditions. Furthermore, the double7 hump characteristics of LDD MOSFET's have been studied by using 27 D numerical slmulation. It has been shown that this phenomenon is due to the fact that the peak generation rate transfers from the channel/n-junction neat the drain side to the gate edge neat the source side. In Chapter 5, the analytic models for the intrinsic and extrinsic charges of conventional and LDD MOSFET's have been presented. In our developed intrinsic charge model, a new parameter has been defined to smoothly connect the intrinsic charges and capacitances at the transition between the linear and saturation regions. In our developed extrinsic charge model,the n-region of LDD MOSFET's has been modeled by three buried7 channel devices with a modified charge sharing scheme. The developed model for the n-region of LDD MOSFET's can also be applied to the n+region of conventional MOSFET's. In order to verify the accuracy of the developed analytic models for the intrinsic and extrinsic charges, a new calculation method for the intrinsic and extrinsic charges using 27 D numerical simulation has been presented. Comparisons of the calculated intrinsic and extrinsic charges between the developed analytic models and the numerical simulations have been made and satisfactory agreements are obtained. In Chapter 6, the major contributions and the proposed future researches have been described.
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