Study on SiGe and SiC Films in MOSFETs and Poly-SiGe and Multi-Channel Poly-Si in TFTs
|關鍵字:||矽鍺;矽碳;化學機械研磨;動態臨限電壓電晶體;薄膜電晶體;SiGe;SiC;Chemical Mechanical Polishing;Dynamic Threshold Voltage MOSFET;Thin-Film Transistors|
|摘要:||本論文提出兩種元件，金氧半場效電晶體和複晶矽薄膜電晶體的製備來驗證薄膜的效應和應用於元件上面的整合度。首先，我們提出在矽鍺(Si0.8Ge0.2)磊晶薄膜中使用化學機械研磨方式來降低晶格不匹配所造成粗糙的表面，我們將全面的研究研磨墊和研磨液對平坦度的影響，接著使用一種新穎的研磨後清洗液應用於表面的清潔，經由加入表面清潔劑(surfactant, TMAH)和螯合劑(chelating agent, EDTA)可以有效的去除表面的微粒子和金屬殘留，表面的粗糙度也可有效的改善至 0.6 奈米。在電性方面，電容的量測可以得到高的崩潰電壓、低的漏電流和較佳的累積崩潰電荷密度；在電晶體的驗證上，可以得到十個百分比的電流增加。接著，探討使用矽碳(Si1-yCy, y=0.005)薄膜於動態臨限電壓電晶體(DTMOS)的應用，經由此介面層引入通道可有效抑制硼原子的擴散，達成高的基底摻雜和低的表面濃度分布。所形成的超陡峭(super-steep-retrograde)通道可使的表面散射(surface scattering)現象降至最低，對於動態臨限電壓電晶體元件有較好轉導(1.2倍)、高的導通電流(1.8倍)和較低的臨限電壓(threshold voltage)表現，可以應用於低電壓操作元件。第二部分我們研究n型複晶矽薄膜電晶體在多重通道(multi-channel)的表現。藉由增加通道的數目以提高閘極的控制能力，可以改善元件的電特性；包括提高導通電流，降低臨界電壓及次臨限擺幅(subthreshold swing)。然而，元件的可靠度卻會因此而變差。我們推測是由於在多重通道的結構中，靠近汲極端的電場強度會增加，而導致更嚴重的碰撞游離(impact ionization)所造成。在論文的最後，我們開發出一種改善複晶矽鍺薄膜電晶體(poly-SiGe TFTs)的製程，經由氨氣的被覆(passivation)可以有效降低溫下矽鍺薄膜通道的缺陷；而經過化學機械研磨對於表面平坦化處理可以有效減低表面的粗糙度，所形成複晶矽鍺薄膜電晶體在結合此兩種處理的最佳化製程，可以得到很好的電性和可靠度表現，達成應用在低溫製程薄膜電晶體的應用。|
In this thesis, two kinds of devices (MOSFETs and TFTs) have been fabricated to examine the films effect and integration of device characteristics. First, the effects of polish pad conditions and slurry solid contents on SiGe chemical mechanical polishing (CMP) process were investigated. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. By adding the surfactant (TMAH) and chelating agent (EDTA) into the diluted ammonium solution, removal efficiency of particles and metallic impurities is increased. The smooth strained-Si surface on flatten Si0.8Ge0.2 buffer layer of 0.6 nm can be achieved. The electrical performances of capacitors such as breakdown voltage, leakage current and Qbd are significantly improved for post-CMP cleaning. Furthermore, the optimal condition of SC1+TE sample has increased about 10 % in drive current. This post-CMP cleaning process is useful for planarization of strain-relaxed SiGe virtual substrates in MOSFET application.Next, we have demonstrated the fabrication of Dynamic Threshold voltage MOSFET (DTMOS) using the Si1-yCy (y=0.005) incorporation inerlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si1-yCy interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. The excellent performances obtained in the Si1-yCy interlayer DTMOS are due to both the same substrate doping concentration and lower channel surface impurity concentration. So the surface impurity scattering could be reduces. We have successfully achieved the low threshold voltage and heavily doped substrate DTMOS with superior characteristics in terms of the higher transconductance (1.2×Gm) and saturation current (1.8×ID). It appears to be a very promising technology for nano-scale device and ultra-low voltage application.Then, we demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon Thin-Film Transistors (poly-Si TFTs) with different numbers of channel stripes. The device’s electrical characteristics, such as on-current, threshold voltage, and subthreshold swing, were improved by increasing the number of channel stripes due to the enhancement of gate control. However, the electric field strength near the drain side was enlarged in multi-channel structures, causing severe impact ionization. Therefore, for the fabrication of highly reliable devices and to improve the yield of multi-channel TFTs, the channel structures must be carefully designed.Finally, the improvement of polycrystalline silicon germanium thin-film transistors (poly-SiGe TFTs) using NH3 passivation and CMP process was examined. Experimental results indicated that NH3 passivation could effectively improve the turn on characteristics. Moreover, the TFTs fabricated on polished poly-SiGe film exhibit higher carrier mobility, better subthreshold swing, lower threshold voltage, and higher on/off current ratio due to the smooth poly-SiGe interface. The results clearly show that by employing the plasma and CMP steps, significant improvement in the poly-SiGe TFTs with low thermal budget can be achieved.
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