標題: Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
作者: Chen, Wen-Yi
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Bipolar-CMOS-DMOS (BCD) process;body current injection;electrostatic discharge (ESD);lateral double-diffused metal-oxide-semiconductor (LDMOS)
公開日期: 1-五月-2010
摘要: The n-channel lateral double-diffused metal-oxide-semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-mu m 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35-mu m 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.
URI: http://dx.doi.org/10.1109/TCSI.2010.2043986
http://hdl.handle.net/11536/5431
ISSN: 1549-8328
DOI: 10.1109/TCSI.2010.2043986
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 57
Issue: 5
起始頁: 1039
結束頁: 1047
顯示於類別:期刊論文


文件中的檔案:

  1. 000278066200009.pdf