CMOS Analog Multipliers and Their Applications
|摘要:||自從第一個以金氧半製成類比乘法器的論文提出以來，各種不同的原理及架構紛紛出現．而新乘法器以改進線性度與加大輸入範圍為首要。基於金氧半電晶體的平方律特性及線性電流電壓轉換，製成無漂移係數且提高線性度的類比乘法器；接著，由四個工作於線性區域電晶體組成乘法器，共有兩個版本的緩衝器以加大輸入範圍；；第三個乘法器獲益於四分之一平方律及差動源極耦合輸入，它具有相當大的輸入範圍；最後，再度以金氧半電晶體的平方方律特性組成無漂移係數的電流乘法器，並有一個新型自動偏壓輸入器可降低電流鏡射的誤差。所有電路均以 3.5微米互補式金氧半製程技術完成晶片，它們的非線性度均小於一個百分比，設計之後，提出成果摘錄與誤差分析，並利用 PSPICE 模擬確認所有結果。|
Since the first paper reported on a MOS analog multiplier in 1982, there are many principles and structures estiblished for those circuits. Improving the linearity and widening the input range are the most important design objectives to build the analog multipliers. A new analog multiplier circuit without the effect of mobility factor to improve the linearity is proposed first. It is based on the square-law I-V characteristic of the MOS transistor and the operation of the linear current-to-voltage converter. The core of the next multiplier is composed of the four transistors operated in linear region. And there are two versions of buffers realized for widening the input range of these linear region multipliers. The quarter-square technique and the differential source-coupled input pairs have gained favor of large input swing in the third multiplier. At last, a current multiplier which is also without the effect of mobility factor is described. A new self-biasing input section of the current multipli r is proposed for lowering nonideal current mirror effect. All circuits are designed and fabricated in the 3.5μm CMOS double-poly single-metal p-well technology. They have a nonlinearity under one percent. Error analysis and performance evaluation have also performed for each multiplier. PSPICE simulations confirm all results.
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