標題: Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications
作者: Sheng, Duo
Chung, Ching-Che
Lee, Chen-Yi
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: ADDLL;DCPS;portable;fast lock;DDR controller
公開日期: 10-五月-2010
摘要: A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90 degrees phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3 degrees at 400 MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides the suitable phase shift of control signals for DDR interface where precise control is the key to reliable high-performance operation. Besides, the cell-based implementation makes it easy to target a variety of technologies as a soft silicon intellectual property (IP).
URI: http://dx.doi.org/10.1587/elex.7.634
http://hdl.handle.net/11536/5411
ISSN: 1349-2543
DOI: 10.1587/elex.7.634
期刊: IEICE ELECTRONICS EXPRESS
Volume: 7
Issue: 9
起始頁: 634
結束頁: 639
顯示於類別:期刊論文


文件中的檔案:

  1. 000278375700012.pdf