Title: A NAND flash memory controller for SD/MMC flash memory card
Authors: Lin, Chuan-Sheng
Dung, Lan-Rong
交大名義發表
電控工程研究所
National Chiao Tung University
Institute of Electrical and Control Engineering
Keywords: Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC);flash storage systems;NAND flash memory controller;nonvolatile memory
Issue Date: 1-Feb-2007
Abstract: In this paper, a novel NAND flash memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash memory chip during the card production stage, the function for supporting various kinds of NAND flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash memory card controller chip was designed and implemented with UMC 0.18 mu m CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.
URI: http://dx.doi.org/10.1109/TMAG.2006.888520
http://hdl.handle.net/11536/5323
ISSN: 0018-9464
DOI: 10.1109/TMAG.2006.888520
Journal: IEEE TRANSACTIONS ON MAGNETICS
Volume: 43
Issue: 2
Begin Page: 933
End Page: 935
Appears in Collections:Conferences Paper


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