標題: Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology
作者: Chen, Shih-Hung
Ker, Ming-Dou
電機學院
College of Electrical and Computer Engineering
公開日期: 1-六月-2010
摘要: NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector. (C) 2010 Elsevier Ltd All rights reserved.
URI: http://dx.doi.org/10.1016/j.microrel.2010.01.030
http://hdl.handle.net/11536/5308
ISSN: 0026-2714
DOI: 10.1016/j.microrel.2010.01.030
期刊: MICROELECTRONICS RELIABILITY
Volume: 50
Issue: 6
起始頁: 821
結束頁: 830
顯示於類別:期刊論文