標題: Low-Complexity All-Digital Sample Clock Dither for OFDM Timing Recovery
作者: Lin, You-Hsien
Hsu, Terng-Yin
資訊工程學系
Department of Computer Science
關鍵字: Low complexity;multiphase clock;orthogonal frequency-division multiplexing (OFDM);phase adjustment;timing recovery
公開日期: 1-七月-2010
摘要: Based on phase adjustment, this work investigates a low-complexity all-digital sample clock dither (ADSCD) to perform coherent sampling for orthogonal frequency-division multiplexing (OFDM) timing recovery. To reduce complexity, only tri-state buffers are acquired to build a multiphase all-digital clock management (ADCM), which can generate more than 32 phases over gigahertz without phase-locked or delay-locked loops. Following divide-and-conquer search and triangulated approximation, the phase adjustment is simple but efficient, such that four preambles are adequate to make analog-to-digital (A/D) sampling coherent. Performance evaluation indicates that the proposed ADSCD can tolerate +/-400-ppm clock offsets with 0.8 similar to 1.3 dB signal-to-noise ratio (SNR) losses at 8% PER in frequency-selective fading. Hence, this scheme involves a little overhead to ensure fast recovery and wide offset tolerance for OFDM packet transmissions.
URI: http://dx.doi.org/10.1109/TVLSI.2009.2019079
http://hdl.handle.net/11536/5221
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2009.2019079
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 18
Issue: 7
起始頁: 1036
結束頁: 1042
顯示於類別:期刊論文


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