標題: High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
作者: Ker, Ming-Dou
Lin, Chun-Yu
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electrostatic discharge (ESD);low-voltage CMOS;mixed-voltage I/O;power-rail ESD clamp circuit;silicon-controlled rectifier (SCR)
公開日期: 1-七月-2010
摘要: For system-on-chip applications with mixed-voltage I/O interfaces, I/O circuits with low-voltage devices must drive or receive high-voltage signals to communicate with other circuit blocks. With the consideration of low standby leakage in nanoscale CMOS processes, a new 2 x V(DD)-tolerant electrostatic discharge (ESD) clamp circuit by using only 1 x V(DD) devices was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of an ESD clamp device, which consisted of a silicon-controlled rectifier (SCR) with a diode in series. This design had successfully been verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only on the order of 100 nA. The test patterns with 25-and 50-mu m SCR-based ESD clamp devices can achieve 2.6- and 4.8-kV human-body-model ESD robustness, respectively. Such high-voltage-tolerant ESD clamp circuits, by using only low-voltage devices with very low standby leakage current and high ESD robustness, were very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.
URI: http://dx.doi.org/10.1109/TED.2010.2049072
http://hdl.handle.net/11536/5173
ISSN: 0018-9383
DOI: 10.1109/TED.2010.2049072
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 57
Issue: 7
起始頁: 1636
結束頁: 1641
顯示於類別:期刊論文


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