Title: Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System
Authors: Wong, Cheng-Chi
Chang, Hsie-Chia
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE);quadratic permutation polynomial (QPP) interleaver;turbo decoder
Issue Date: 1-Jul-2010
Abstract: This brief presents a parallel architecture for the turbo decoder using the quadratic permutation polynomial inter-leaver. The supported block size ranges from 40 to 6144 with an increment of 8, and thus, it includes 188 sizes in the 3rd Generation Partnership Project Long Term Evolution standard. The proposed design can allow one, two, four, or eight soft-in/soft-out decoders to process each block with configurable iterations. To support all data transmissions in the parallel design, a multistage network with low complexity is also utilized. Moreover, a robust path metric initialization is given to improve the performance loss in small blocks and high parallelism. After fabrication in the 90-nm process, the 2.1-mm(2) chip can achieve 130 Mb/s with 219 mW for the size-6144 block and eight iterations.
URI: http://dx.doi.org/10.1109/TCSII.2010.2048481
http://hdl.handle.net/11536/5170
ISSN: 1549-7747
DOI: 10.1109/TCSII.2010.2048481
Journal: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 57
Issue: 7
Begin Page: 566
End Page: 570
Appears in Collections:Articles


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