Title: A CMOS mismatch model and scaling effects
Authors: Wong, SC
Pan, KH
Ma, DJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Issue Date: 1-Jun-1997
Abstract: In this letter, a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model, Mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches, SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations, In addition, a root n-law model is developed for modeling gate-finger dependence of mismatch.
URI: http://dx.doi.org/10.1109/55.585349
http://hdl.handle.net/11536/517
ISSN: 0741-3106
DOI: 10.1109/55.585349
Journal: IEEE ELECTRON DEVICE LETTERS
Volume: 18
Issue: 6
Begin Page: 261
End Page: 263
Appears in Collections:Articles


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