標題: A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
作者: Chen, Chia-I
Huang, Juinn-Dar
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: multicycle communication;architectural synthesis;high-level synthesis;performance-driven;criticality-driven
公開日期: 1-七月-2010
摘要: In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
URI: http://dx.doi.org/10.1587/transfun.E93.A.1300
http://hdl.handle.net/11536/5151
ISSN: 0916-8508
DOI: 10.1587/transfun.E93.A.1300
期刊: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Volume: E93A
Issue: 7
起始頁: 1300
結束頁: 1308
顯示於類別:期刊論文


文件中的檔案:

  1. 000281342900003.pdf