標題: Efficiency improvement in charge pump circuits
作者: Wang, CC
Wu, JC
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
關鍵字: charge pump;CMOS analog integrated circuit;latch-up
公開日期: 1-Jun-1997
摘要: Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25 kHz with 12 mA loading on both inverting and noninverting outputs. The switching frequency is automatically reduced when loading is lighter to improve the power efficiency. The frequency tuning range of this circuit is designed to be from 100 Hz to 25 KHz. A start-up circuit is included to ensure proper pumping action and avoid latch-up during power-up. A slow turn-on, fast turn-off driving scheme is used in the clock buffer to reduce power dissipation, The new dual charge pump circuit was fabricated in a 3-mu m p-well double-poly single-metal CMOS technology with breakdown voltage of 18 V, the die size is 4.7 x 4.5 mm(2), For comparison, a charge pump circuit with conventional level shifter and clock buffer was also fabricated. The measured results show that the new charge pump has two advantages: 1) the power dissipation of the charge pump is improved by a factor of 32 at no load and by 2% at rated loading of 500 Omega and 2) the breakdown voltage requirement is reduced from 19.2 to 17 V.
URI: http://dx.doi.org/10.1109/4.585287
http://hdl.handle.net/11536/513
ISSN: 0018-9200
DOI: 10.1109/4.585287
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 32
Issue: 6
起始頁: 852
結束頁: 860
Appears in Collections:Articles


Files in This Item:

  1. A1997XA68600009.pdf