標題: On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes
作者: Lin, Chia-Yi
Lin, Hsiu-Chuan
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Compression;DFT;low power;scan chain;test data volume
公開日期: 1-八月-2010
摘要: In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.
URI: http://dx.doi.org/10.1109/TVLSI.2009.2021061
http://hdl.handle.net/11536/5117
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2009.2021061
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 18
Issue: 8
起始頁: 1220
結束頁: 1224
顯示於類別:期刊論文


文件中的檔案:

  1. 000282380600007.pdf