|標題:||On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes|
Department of Electronics Engineering and Institute of Electronics
|關鍵字:||Compression;DFT;low power;scan chain;test data volume|
|摘要:||In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.|
|期刊:||IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS|
|Appears in Collections:||Articles|
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