標題: 半導體3DIC發展之專利分析與技術預測評估
Technological Forecast and Patent Analysis of 3DIC
作者: 盧景睿
袁建中
管理學院科技管理學程
關鍵字: 3DIC封裝;3DIC;TSV
公開日期: 2011
摘要: 半導體的製程在將近四十年的發展一直都遵循著摩爾定律 (Moore’s law) ,然而目前半導體發展到28奈米或20奈米製程則遇到製程困難及成本的考量,加上目前的消費性的產品不再以PC為主,取而代之的是輕薄的行動通訊或掌上型平版電腦,其內部的半導體構裝技術則以整合性及薄化為主。3DIC TSV構裝技術則為整合性及薄化封裝的最終極的產品。3DIC為近年來各大半導體廠開發的構裝技術,其利用微小凸塊當作晶片之間的導線,使得晶片之間的傳輸速度更快、雜訊更少、減少晶片消耗功率。其晶片堆疊之結構亦減少封裝的體積,正可驅動整體消費性電子市場的開發與需求。3DIC目前仍有許多製程困難挑戰需克服,而各大半導體廠在開發及申請美國專利上亦呈現成熟飽和之階段,目前半導體廠及封裝廠則以2.5D為開發主流,在2013年有機會先量產。而3DIC也在未來幾年內會出現在市場,為電子市場帶來一次新的革命機會。
Moore’s law has been proven effectively over 40 years as the transistors on the wafer doubled the density in eighteen months while lithography technology successfully moved forward to scale the design. However, the lithography faced its limitation as the CMOS technology moved to 28 nm or 20 nm while multiple patterning increased the cost dramatically that foundries or IDMs realized this challenge and then developed the three-dimension chips (3DIC) using through silicon via (TSV) to increase I/O interconnection and design density. 3DIC has its advantages in terms of electrical performance and form factor that thin, integrated chips can replace the current consumer chips or system modules to satisfy the current mainstream of handheld or PAD products. 2.5D is also the major development among semiconductor companies that plan to have volume production in 2013. The electronics market will face revolutionary change once 3DIC has been adopted to replace current packaging in coming years.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079965518
http://hdl.handle.net/11536/50788
Appears in Collections:Thesis