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dc.contributor.author陳君彥en_US
dc.contributor.authorChun, Chun-Yenen_US
dc.contributor.author徐慰中en_US
dc.contributor.authorHsu, Wei-Chungen_US
dc.date.accessioned2015-11-26T01:04:08Z-
dc.date.available2015-11-26T01:04:08Z-
dc.date.issued2013en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079955550en_US
dc.identifier.urihttp://hdl.handle.net/11536/50465-
dc.description.abstract本篇論文是透過動態二進制轉譯相關技術嘗試改良微架構內快取記憶體模擬之機制。有鑑於快取記憶體在微架構模擬中影響效能的權重,此實驗將關注在如何改善其效能。其中將修改SimpleScalar並透過此一平台進行實驗。當測試的程式,例如迴圈等重複執行且內含許多需存取記憶體的指令時,其中會產生許多不必要的快取記憶體模擬。經由本實驗設計的方法,可偵測並進一步減少快取記憶體模擬的次數以使整體效能提升。實驗結果顯示,改良後的SimpleScalar在執行快取記體憶模擬時的平均時間比起原本快上了3.4~3.9倍zh_TW
dc.description.abstractThis thesis uses DBT techniques to improve the performance of micro-architecture’s cache mechanism. This study will focus on how to improve cache simulation’s performance due to the cache importance in micro-architecture simulations. We modified the SimpleScalar and ran the experiment on it. When running the test codes with many memory reference instructions, such as loops, repeatedly, there are many redundant cache simulations. By our experiment method, these redundancies will be detected and the times of cache simulations will be reduced. With the enhancement and associated optimization, we have observed 340%~390% of speed up on average over the original SimpleScalar.en_US
dc.language.isoen_USen_US
dc.subject微架構zh_TW
dc.subject快取記憶體zh_TW
dc.subjectmicro-architectureen_US
dc.subjectcache simulationen_US
dc.subjectDBTen_US
dc.title利用動態二進制轉譯技術改善微架構內快取記憶體模擬:個案研究zh_TW
dc.titleUsing DBT (Dynamic Binary Translation) to improve performance of micro-architecture’s cache simulations: a case studyen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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