標題: 減少嵌入式處理器之程式記憶體的資料匯流排耗電
Power Minimization in the Program Memory Data Bus for Embedded Processors
作者: 鄭欽宗
Chin-Tzung Cheng
單智君
Jean, J.J Shann
資訊科學與工程研究所
關鍵字: 崁入式系統;省電;匯流排編碼;位元變化;Embedded system;Low power;Bus encoding;Bit transition;BIBITS
公開日期: 2003
摘要: 隨著嵌入式處理器快速發展,省電考慮也日益重要。由於off-chip匯流排耗電佔了整體系統的耗電蠻大部分,許多研究已經著重在如何減少off-chip匯流排的電耗。因為匯流排上的電耗大約成正比於其上傳送的資料位元變化量,所以減少匯流排上的位元變化量是降低匯流排電耗的一個有效的方法。 目前已經有許多減少位址匯流排電耗的研究被提出,然而減少資料匯流排電耗的方法卻很少。因此針對目前嵌入式處理器在程式記憶體的資料匯流排上電耗,我們提出BIBITS匯流排編碼方法來減少程式記憶體的資料匯流排上電耗。我們也提出modified register relabeling結合BIBITS匯流排編碼方法,使編碼過後的程式,在程式記憶體的資料匯流排上傳送時的位元變化量更小。 根據實驗數據結果顯示,我們提出的方法比完全都沒做過編碼的情況平均減少了64% 的bit transition,比起單純只有register relabeling 多出約57% 的 bit transition減少量,比起Petrov提出的方法多出約16% 的bit transition減少量。而且我們的方法在針對全部基本區塊(basic-block)編碼所需要儲存的資料約只要Petrov提出的方法的一半。並且我們的方法在解碼電路的實作比他的方法簡單。整體而言,這項研究成果在嵌入式處理器上能有更進一步的省電效果。
Reducing the power consumption of embedded processor has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as they consume a significant amount of total power. Reducing the bus switching is an effective way to reduce bus power since the bus power consumption is about proportional to the switching activity. While numerous techniques exist for reducing bus power in address buses, only a handful of techniques have been proposed for data-bus power reduction. For the low power requirement on the program-memory data bus of current embedded processors, we proposed a BIBITS bus encoding scheme to reduce power consumption on program memory bus. A modified register relabeling algorithm is also proposed to be combined with BIBITS bus encoding scheme to further reduce bit transitions. These techniques aim at reducing more switching activity and hence, more power consumption. The simulation results showed that the overall average switching reduction is 64% over original data and 57% more than original register relabeling scheme only and 16% more than Petrov’s bus encoding scheme only. Contrary to Petrov’s bus encoding scheme, our proposed scheme need only a half transformation table size to encode all basic blocks. Moreover, our decoder implementation is simpler than theirs. Therefore, the extra hardware overhead of our proposed is lower than Petrov’s bus encoding scheme. We can conclude with certainly that our research results may have more power saving opportunities.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009117576
http://hdl.handle.net/11536/50158
Appears in Collections:Thesis