標題: Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
作者: Tu, Ming-Hsien
Lin, Jihi-Yu
Tsai, Ming-Chien
Jou, Shyh-Jye
Chuang, Ching-Te
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Low power;low voltage;single-ended SRAM
公開日期: 1-Dec-2010
摘要: In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V(DD), an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 mu W.
URI: http://dx.doi.org/10.1109/TCSI.2010.2071690
http://hdl.handle.net/11536/5014
ISSN: 1549-8328
DOI: 10.1109/TCSI.2010.2071690
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 57
Issue: 12
起始頁: 3039
結束頁: 3047
Appears in Collections:Conferences Paper


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