標題: 視訊編碼器在雙核心平臺上的最佳化
Video Codec Optimization for Dual-core Architectures
作者: 曾建堂
Chien-Tang, Tseng
蔡淳仁
Chun-Jen, Tsai
資訊科學與工程研究所
關鍵字: 雙核心;視訊;編碼;平行;omap;mpeg4;encoder;dual-core;parallel
公開日期: 2003
摘要: 在本篇論文中,我們提出一個方法使MPEG-4 Simple Profile視訊編碼器在雙核心(RISC以及DSP)平臺上的執行能更具效能。在目前視訊編碼器對於RISC核心以及DSP核心的使用,運算重心是以DSP核心為主。但隨著RISC運算能力的強化,未來RISC核心也將有足夠的能力來處理繁重的運算。因此,我們藉著評估分析視訊編碼器中各主要元件的運算特性,建立出一套能動態分配工作至各運算單元使之平行運算的雙核心視訊架構。而為了解決雙核心之間資料傳輸的負擔,該架構中也使用DMA的機制來改進效能。而從實作結果證實,在使用我們的雙核心視訊架構後,視訊編碼器效能將因此提升。
In this paper, we propose a dynamic task partitioning framework on dual-core architecture (RISC and DSP) for the MPEG-4 Simple Profile video codec. Using a dynamic task scheduler, an efficient dynamic partitioning framework of video encoder algorithm on dual-core architecture are developed. Existing practices of embedded software development on a dual-core platform either assign a subtask to the RISC core or the DSP core. However, since new generations of RISCs are powerful enough for computationally intensive task as well, the proposed framework will invoke both the RISC and the DSP cores in parallel to complete a single subtask in a tightly-coupled manner. To alleviate the communication overhead between the two cores, DMA is used to transfer data between the MCU and the DSP. From the experiments, it is shown that the proposed approach achieves higher performance than the conventional approach where only one of the cores (either MCU or DSP) is used for each subtask.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009117559
http://hdl.handle.net/11536/49990
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