A Unified 3D Device Simulation of Intrinsic Parameter Fluctuation on High-k/Metal Gate Bulk FinFET Device
|關鍵字:||鰭式場效應電晶體;內部參數擾動;3D Device Simulation;High-k/Metal Gate Bulk FinFET Device;Intrinsic Parameter Fluctuation|
|摘要:||近年來，根據國際半導體技術藍圖(ITRS romap)，電晶體尺寸不斷的微縮，已經來到次奈米級世代，各種製程步驟皆更加的繁雜，每個步驟背後需要仰賴更多技術的克服，因此若想要電晶體得以維持摩爾定律(Moore’s Law)繼續微縮，除了傳統製程技術上的突破創新，電晶體結構上的創新，是次奈米級甚至奈米級電晶體勢必要有的革新，而在這些千奇百怪、天馬行空的幾何新結構中，又以鰭式場效應電晶體(FinFET)最符合公司成本上的需求並且有效提升電晶體電特性不只一個世代。另外使得摩爾定律能夠延續的一項非常重要技術金屬閘極與高介電係數閘極絕緣材料，它已經是奈米級電晶體元件開發不可或缺的技術，然而，伴隨著這些結構的創新技術的改良，是否衍生出新的擾動來源，而傳統的擾動來源於新結構中是否得以壓抑等，都是學術界、工業界非常關切的議題。本論文提出有效的模擬方法，探討製程變異，以及隨機參數的擾動於鰭式場效應電晶體的影響，相較於傳統電晶體將獲得多少改進，並且探討將種種擾動來源同時考慮後對於電晶體的影響。
For these years, according to ITRS roadmap, the size of device keeps scaling. It comes to nanodevice’s generation, each step of process technology has became more complicated, and they based on more breakthrough of technology. If we want to keep scaling based on Moore’s Law technology, In addition to the breakthroughs and innovations for traditional process technology, the innovation of transistor structure for sub-nano-or even nanoscale transistors is the key-point. In those strange, or abstract geometric new structure, the FinFET transistor outstandingly conform the demands of costs for company, and it effectively improve the characteristics of transistors to next generation even batter. To keep the Moore’s Law be continued, there is a very important technology; high-□ metal gate technology. And, it has become indispensable technology for the development of nanoscale transistors. No matter the part of academia or industry, we all wonder to know whether the traditional fluctuated source is suppressed by new device structure, and whether there are new fluctuated source accompanied with the innovation of new structure. This paper presents an effective simulation method to investigate the impact of process variation, and random parameter effect for FinFET structure, we would investigate the extent of improvement compared to traditional planar transistor, and we also research that put all the different fluctuated source into one transistor, then investigate the reference between all different fluctuated sources. In this study, we do the experiment of device simulation with Monte Carlo method for three-dimensional transistor, for the part of device process variation, and due to the FinFET structure is three-dimensional transistor, we would investigate the influences of transistor from the channel length, width and high variation. We found there are different degree of relationships between each component of variability and threshold voltage. After the analysis, the result shows that there are different slopes of the linear proportion between each variation and threshold voltage. Finally, we discuss each component was considered in one transistor, we can simulate more closely to the situation of real process by this way. This study provides the academia and industry a basis that process variation induced fluctuation for nanoscale transistor, and we investigate the trends from the variations induced fluctuation of transistor characteristic, by the trends we provide some idea for suppressing technology. For the part of random parameter, we discuss three fluctuated sources: random interface traps, random dopants and random workfunction variation. In the part of random dopants, we generate three-dimensional dopants in the channel based on Gaussian distribution, and analyze each device for different distribution of dopants; in the paet of random interface traps, we applied similar simulation method, we randomly generate two-dimensional traps divided into each device, to analyze the phenomenon of traps between channel and insulator of high-k material. And, both these two fluctuated source, we completely examined the effects RDs and Its number and position on device characteristic fluctuations including threshold voltage, on-/off-state current, maximum transconductance, output resistance of transistor, drain induced barrier lowering, gate capacitance. For the part of random workfunction fluctuation, we applied localized workfunction simulation method which is different from the traditional average workfunction simulation method, it could effectively simulate the situation of actual process. We investigate the metal lattice size, location, quantity, resulting in DC characteristics fluctuation, and explore ways to improve structure for suppressing fluctuation. Finally, we simultaneously consider the effects of RDs, Its and WKs, and we compare the characteristic between the planar transistor and FinFET structure, we examined each suppression of fluctuated sources, and try to know most effective transistor is composed in which geometric proportions. In summary, this paper analyzes the process variation including gate length, width, and height defects; we also examine the random effects including RDs, Its and WKs. We completely analyze all chiefly fluctuated sources inducing transistor variability, and to further explore the situation when each fluctuation considered in one transistor, to compare the suppression between traditional planar transistor and FinFET structure transistor. We believe the results of this study are useful for the characteristic analysis of next generation transistor.
|Appears in Collections:||Thesis|