標題: 應用在叢集式超長指令集處理器的叢集間低成本通訊方法
A Low-Cost Inter-cluster Communication Scheme for Clustered VLIW Processors
作者: 吳智斌
Chih-pin Wu
鍾崇斌
Chung-Ping Chung
資訊科學與工程研究所
關鍵字: 超長指令集處理器;叢集化;叢集間通訊;暫存器檔案;VLIW;Clustering;Inter-cluster communication;Register File
公開日期: 2003
摘要: 在超長指令集處理器上,叢集化是一個常被利用來幫助實作 Register File 的一個方法。若沒有叢集化,當加入了大量的 Function Units 到超長指令集處理器上後, 對 Register File 的讀寫埠需求會使得 Register File 的存取延遲、面積和耗電成為一大問題。 然而即使是使用了叢集化的技巧,淚{存的幾個叢集間通訊方法仍需要依賴額外的讀寫埠讓各叢集交換資料。本文提出了一個不需要額外的讀寫埠也可以達到叢集間通訊的方法;我們以將暫存器實作成讀寫埠分別面對不同的叢集的方式來達成叢集間通訊。由於不用增加額外的讀寫埠和投資新的硬體資源,這種方法可以在存取延遲、面積和耗電方面上較現有的方法具有優勢,並讓叢集式超長指令集處理器可以用一個較低成本的方法達到叢集間通訊的目的。
Clustering is a well-known technique to improve the implementation of register file on VLIW processors. Without clustering, high demands on read/write ports will bring many issues on power dissipation, area and delay, and thus makes the hardware scalability problematic. However, most inter-cluster communication models rely on extra read/write ports to access register values between clusters. The objective of the thesis is to propose an inter-cluster communication model which demands no extra read/write ports but using a kind of single-way special register. We evaluated the performance by hand-optimized codes and code rewriting generation approach. Simulated results showed that for several generic computation kernels, only a few extra cycles and special registers will be needed, but sacrificing no extra delay on register file access. Thus improvements on execution time can be achieved. The design will also benefit from less power dissipation and fewer silicon area, making the approach an efficient and economic communication scheme for clustered VLIW processors.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009117524
http://hdl.handle.net/11536/49646
Appears in Collections:Thesis


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