標題: 電容式加速度計暨電容轉數位介面電路設計
Capacitive accelerometer with capacitance to digital interface circuit design
作者: 王竣傑
Wang, Chun-Chieh
溫瓌岸
Wen, Kuei-Ann
電子研究所
關鍵字: 電容式加速度計;電容轉數位電路;互補式金屬氧化物場效電晶體暨微機電系統;Capacitive accelerometer;Capacitance to digital Circuit;CMOS MEMS
公開日期: 2012
摘要: 本論文提出一建立在混合信號微機電製程下具電容轉數位讀出電路之單晶加速度計設計。加速度計操作範圍設計在-5g到5g內,電容變化為441.2fF到470fF,敏感度2.88fF/g,利用電容轉脈寬電路讀取此範圍電容值,能達到靈敏度為6.94us/pF,相當於20ns/1bit,因此在不須任何類比轉數位電路情況下,能轉出為數位訊號,以便後續數位訊號處理。為了從整合的前端電路取得精準值,採用感測器電腦輔助設計軟體與電子設計自動化軟體模擬整合後的電路暨加速度計,具體分析模擬與實際量測差異處,並完成微機電製程與積體電路整合設計流程。
A monolithic accelerometer with integrated capacitance to digital readout circuit in 0.18um CMOS MEMS process is proposed to demonstrate sensor to bit integration. The sensing range of the accelerometer is designed from -5g to 5g and the variation of the capacitance is from 441.2fF to 470fF. The sensitivity of the accelerometer is 2.88fF/g. The capacitance value of the sensing range is readout by the capacitance to pulse-width circuit to readout. The capacitance to pulse-width circuit of the sensitivity is 6.94us/pF which is equivalent to 20ns/1bit. Therefore, without any analog to digital module, the output signal can be directly interface to digital signal process. In order to get the accurate value of monolithic front-end circuits, the computer aided design flow for MEMS and IC integration is used to co-simulate the monolithic circuits with the accelerometer and to provide comprehensive analysis of the difference between the simulation and the measurement results.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079911683
http://hdl.handle.net/11536/49199
Appears in Collections:Thesis


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  1. 168301.pdf