標題: 單晶片微加速度計與可調式靈敏度讀出電路整合設計
Design of a Monolithic Micro-accelerometer with a Readout Circuit of Tunable Sensitivity
作者: 林易達
Lin, Yida
溫瓌岸
Wen, Kueiann
電子研究所
關鍵字: 加速度計;可調式增益放大器;雙截波穩定放大器;雙相關取樣;三角積分類比數位轉換器;Accelerometer;Variable Gain Amplifier (VGA);Dual-chopper Amplifier (DCA);Correlated Double Sampling (CDS);Sigma-Delta ADC
公開日期: 2012
摘要: 本論文提出一單晶片微加速度計與可調式靈敏度讀出電路整合設計,此感測系統在標準0.18um製程下製作。藉由讀出電路可調增益的功能可以使此感測系統更廣泛的應用在各種不同的加速度環境。本論文的低雜訊可調增益前置放大器採取開迴路的連續時間電壓感測並採取二次截波穩定搭配雙相關取樣解調功能以達到抑制低頻雜訊和直流偏移誤差的目的,最後經由三角積分類比數位轉換器將訊號數位化。根據模擬結果,可調靈敏度範圍從324.8 mV/fF 到17425.47 mV/fF,訊號對雜訊諧波失真比82dB,有效位元12位元。根據量測結果,前置放大器電路的等效輸入加速度雜訊可以被抑制到29.41ug/√Hz,總功耗1.043mW。
The accelerometer is fabricated in 0.18µm ASIC-compatible CMOS MEMS technology and, with the assistant of low noise gain tunable interface being combined with 2nd Sigma-Delta Modulator (SDM) A/D converter in the proposed work. The linear decibel variable gain amplifier (VGA) can regulate the output signal level between sensor signals and external forces. It makes the newly proposed monolithic CMOS MEMS accelerometer with low noise gain tunable interface more applicable to various applications. The new approach of the low noise preamplifier combines the Dual-Chopper amplifier (DCA) and Correlated Double Sampling (CDS) demodulation technologies to alleviate 1/f noise and DC offset. According to the simulation results, the tunable sensitivity can be adjusted from 324.8mV/fF to 17425.47mV/fF in differential mode. SNDR is 80dB, ENOB is 12bit. According to the measurement results, The circuits noise equivalent acceleration (CNEA) is 29.41ug/√Hz. The total power consumption is limited to 1.043mW.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079911679
http://hdl.handle.net/11536/49196
Appears in Collections:Thesis


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