標題: N型多晶矽薄膜電晶體元件製作與高頻特性分析
Fabrication and High-Frequency Characterization of N-type Poly-Si Thin-Film Transistors
作者: 林廷燿
Lin, Ting Yao
林鴻志
黃調元
Lin, Horng Chih
Huang, Tiao Yuan
電子研究所
關鍵字: N型多晶矽薄膜電晶體;光阻微調技術;小訊號參數;小訊號模型;截止頻率;n-type poly-Si thin-film transistors;photoresist-trimming techniques;small-signal parameters;small-signal model;cut-off frequency
公開日期: 2012
摘要: 本篇論文中,吾人製作N型薄膜電晶體元件並研究其高頻特性。高頻特性容易受到寄生效應的影響,因此降低寄生效應為特性好壞的主要關鍵。此薄膜電晶體使用了矽化鎳來降低源極、汲極和閘極的接觸電阻,另外也利用了過度曝光與光阻微調技術微縮了閘極的長度來改善高頻特性。我們還發現在多指型閘極結構中,雙重微影成像技術容易造成閘極長度的誤差,使得在關閉狀態時電流會傾向從較短的閘極長度處漏走。 此外,我們成功的藉由小訊號模型萃取出小訊號參數,由S參數比較模擬與量測結果,證實了小訊號模型的正確性。與單一閘極結構的小訊號參數相比,我們可以發現在多指型閘極結構中的寄生電阻會變小,寄生電容會增加,但整體來說對改善截止頻率與最大震盪頻率還是有利的。雖然外部阻抗很大而且可能會影響到實際的交流性能,但是由模擬結果證實是可信的。歸一化量測值與模擬結果做比較,可明顯發現兩者趨勢是相符的。
In this thesis, we have fabricated n-type poly-Si thin-film transistors (TFTs) and studied their high frequency characteristics. High frequency characteristics are affected easily by the parasitic components, hence reduction of these components is essential. Resistances of source, drain, and gate are reduced with the aid of Ni silicidation technique in this work. To effectively shrink the gate length, we used both over-exposure and photoresist-trimming techniques to shrink the dimension of the PR patterns. These actions are helpful in improving the high frequency characteristics. However, we found the fluctuation in the dimensions of the interdigital poly-Si gate patterns fabricated by double-pattering process is significant. The anomalously shortened gate lengths in the interdigital gate structures tend to increase the off-state current. We’ve also successfully extracted the small-signal parameters by using a small-signal model. The simulation results of S parameters agree well with the measured data, confirming the accuracy of the small-signal model. As compared with the device with single-gate pattern, the values of parasitic resistances become smaller and the values of parasitic capacitances increase in the interdigital gate structure. But it is still beneficial for improving cut-off frequency and maximum oscillation frequency with the interdigital gate structure. Although the extrinsic resistances are large and may affect the practical ac performance, the analysis is confirmed with the simulation results and proved to be reliable. From both the normalized data and the comparison of the experimental results with the simulation, it is observed that the trends of calculation agree well with the measurements.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079911558
http://hdl.handle.net/11536/49105
Appears in Collections:Thesis


Files in This Item:

  1. 155801.pdf